The DesignWare® ARC® Fast Floating Point Unit (FPU) adds performance efficient half-precision, single-precision, and double-precision hardware acceleration for floating point math instructions to all ARC HS4x processors, including ARC HS44, HS45D, HS46, HS47D, and HS48, as well as dual-core and quad-core versions. The FPU accelerates high-precision computation on data sets with a large dynamic range. Table 1 on page 2 lists names and functions of single-precision floating point instructions.
When used with the ARC MetaWare C/C++ Compiler, the ARC HS Fast FPU complies with the IEEE-754-2008 Standard for binary floating point arithmetic. The ARC HS4x processors combined with the FPU provide an ideal solution for system-on-chips (SoCs) that perform complex computations or control algorithms, especially where power and area budgets are constrained.
Small Die Area and Power´
The Fast FPU is implemented as an integral part of the dual-issue ARC HS4x pipeline with full dependency checking and operand bypass capabilities. In contrast to the large floating point coprocessors required by competitive cores, the ARC HS Fast FPU instructions are integrated into the ARC HS4x processor pipeline. This unique approach achieves comparable floating point performance to a coprocessor, but with significantly smaller die area and power consumption. The FPU is implemented so that it will be gated off when not active, further lowering power consumption.
The DesignWare ARC C/C++ Compiler math library optimizes performance and takes full advantage of the ARC FPU instructions to accelerate transcendental and other functions specified in IEEE 754-2008