Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
FCRAM I Controller
Lattice's FCRAM I controller core provides a simple and flexible solution to interfacing different FCRAM I memories to user application logic. On the memory side, the FCRAM I controller core interfaces to FCRAM I data bus widths with (configurable) 8 or 16 bit DDR memory interfaces. On the user side the core provides a simple command interface that accepts read, write, and refresh commands. The core interfaces to 256 Mbit FCRAM I devices (speed grades -60/CAS latency 3 and 4 and -55/CAS latency 3).
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Block Diagram of the FCRAM I Controller IP Core
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