Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol size is ‘m’ bits for all Galois Field operations
Every symbol and primitive polynomial used of degree ‘m’ and ‘n’ is ((1<<‘m’)-1) .Shortened ‘n_short’ is less than ‘n’ where symbols (‘n’ – ‘n_short’) are 0 . If the code has ‘t’ error correcting capability then ‘k’ = ‘n’ – 2*’t’=no. of message symbols. Here 2*’t’ erasures can be recovered.
RTL is completely configurable for ‘m’ , ‘n_short’ or ‘t’. Typically, but not necessarily ‘m’ lies between 5 to 15
ECC, number of parity symbols is 2*’t’.
Errors_correctable = floor((2*tt-no_eras)/2)
The Erasure correcting Code consists of:
A. It has programmable input data bus width. The whole encoding can be completed in 0 cycle
A. Phi Calculator: It takes in erasure locations and number of erasures and generates phi
B. Syndrome Calculator: It can generate all syndromes in 0 clocks, or serially in as large as ‘n_short’ clocks
C. BerlekampMasy Circuit: it generates error locator polynomial for Chien search engine
D. Parallel Chien Search Engine: It finds error locations in as little as 0 clock or as large as ‘n_short’ clocks
E. Forney Circuitry: It can give the symbol to correct the data at error location indicated by Chien Engine.
If RS is configured for 16 bits of error correction, then the same decoder/encoder can be used for any number of bit corrections from 1 to 15
This way the overhead can be reduced if desired.