SMS3000 is a fully integrated CMOS transceiver compliant with ANSI X3T11 Fiber Channel standards. It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, High-speed, Low jitter PECL serial input-output interface, Comma detect for 8B/10B encoded data frame alignment functionality’s. Digital controller interface is realized with 10-bit parallel operation which allows use of 125/106.25 Mhz reference Clock. The transceiver includes extensive Analog and digital Signal Detect capability which indicates valid signal presence at its receive inputs, through verification of valid 8B/10B characters, and valid control ( K ) character occurrence at permitted intervals. Signal Detect also aids automatic lock to reference feature.
SMS3000 through on-chip programmable cable equalizer circuitry enable extended reach copper cable connections and enhanced robust operation in case of heavily attenuated, distorted receive signals. The system signal integrity is enhanced by on-chip programmable transmit pre-equalizer function, which allows the transceiver to be suitable for several package and system design environment.
SMS3000 does not require any external Loop filter capacitor (s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution.
- 1.065 Gigabit/s ANSI X3T11 Fibre Channel Compliant
- 10Bit Controller interface for receive and Transmit data paths
- Inherently Full Duplex Operation
- PECL Reference Clock option
- Frequency comparison and auto-lock to reference
- Programmable Receive Cable Equalization
- Requires No External Loop Filter Capacitors
- Transmit Jitter and distortion minimization through programmable transmit equalizer
- Embedded Bit Error Rate Testing (BER) Through PBRS Generation and Detection
- Proprietary Phase Detector allows superior receive jitter performance
- Driver Compatible with Both 75 and 50 Ohm terminations
- Full Low Cost, Low Power CMOS Implementation
Block Diagram of the Fibre-Channel Transceiver IP Core