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NB-IoT Protocol Stack IP (3GPP CAT-NB1, L1-L3 and Service Layer)
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Flash Memory LDPC Error Correction
The Xilinx® LogiCORE™ IP Flash Memory low-density parity-check (LDPC) Error Correction core is a major component for improving flash reliability. It implements the encoding and decoding functions for cloud and data center storage applications. The core utilizes advanced code construction methodology and proprietary optimization technique to achieve best code performance and low error floor. It is also designed with high resource efficiency and low latency and can be targeted to Virtex®-7, Kintex®-7, Virtex UltraScale™, and Kintex UltraScale devices
Features
- Best-in-class code performance near Shannon limit
- Achieved low error floor under 1e-15 with proprietary optimization method
- Support for code rate change on-the fly
- Support for both hard decision and soft decision decoding
- High throughput and low latency performance
- FPGA optimized for minimal area and power
- Provides decoder status and statistics interfaces
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