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100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
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Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while reading from the storage devices. Decoding corrects read errors. The LDPC code that is used with storage devices should exhibit very low error floor (very low BER) and have high throughput.
Features
- Quasi cyclic (QC) – Algebraic constructed – LDPC code
- Regular parity check matrix
- Codeword length: 16 K
- Code rate: 0.953
- No or very low error floor
- Minimum sum algorithm
- Parallel/ Layered decoding
- Soft decision decoding
- Configurable number of iterations
Deliverables
- System Matlab model
- Synthesizable Verilog RTL
- Test Benches for verification
- Documentation
Applications
- Flash Memory
View Flash Memory LDPC full description to...
- see the entire Flash Memory LDPC datasheet
- get in contact with Flash Memory LDPC Supplier