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FlexNoC 5 Network on Chip (NoC)
Arteris IP FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automotive, consumer, enterprise, and other applications.
With Arteris FlexNoC 5 interconnect IP, engineers achieve reduced wiring congestion, larger timing margins, and lower power consumption, as well as improved productivity and design quality through a set of intuitive and powerful development tools.
FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today's SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.
With Arteris FlexNoC 5 interconnect IP, engineers achieve reduced wiring congestion, larger timing margins, and lower power consumption, as well as improved productivity and design quality through a set of intuitive and powerful development tools.
FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today's SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.
View FlexNoC 5 Network on Chip (NoC) full description to...
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Block Diagram of the FlexNoC 5 Network on Chip (NoC) IP Core
Video Demo of the FlexNoC 5 Network on Chip (NoC) IP Core
Understanding how on-chip interconnect and DDR memory controller configurations impact the system performance, power and cost of multicore SoCs requires deep visibility. Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with the deep, system-level analysis they need to configure and optimize Quality-of-Service (QoS) features earlier in the design cycle.
NoC interconnect IP
- Ncore 3 Coherent Network on Chip (NoC)
- High speed NoC (Network On-Chip) Interconnect IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- FlexNoC 5 Option For Scalability and Performance Critical Systems
- Scalable Cache Coherency
- AMBA 5 / AXI / ACE / ACE-lite / CHI NoC monitor