FlexNoC 5 Option For Scalability and Performance Critical Systems
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Video Demo of the FlexNoC 5 Option For Scalability and Performance Critical Systems
Understanding how on-chip interconnect and DDR memory controller configurations impact the system performance, power and cost of multicore SoCs requires deep visibility. Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with the deep, system-level analysis they need to configure and optimize Quality-of-Service (QoS) features earlier in the design cycle.
NoC interconnect IP
- FlexNoC 5 Network on Chip (NoC)
- Ncore 3 Coherent Network on Chip (NoC)
- High speed NoC (Network On-Chip) Interconnect IP
- Network-on-Chip (NoC) Interconnect IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- Scalable Cache Coherency