Arteris IP FlexNoC AI Package accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and optimize the networks while efficiently implementing multicast and physical design.
- Scales from 10s to 100s of IP blocks
- Automatically generates ring, mesh and torus networks
- View and edit generated topologies
- Edit and optimize individual network routers
- Multicast writes for efficient data broadcast
- Source synchronous communications for long data paths eases clock tree synthesis
- VC-Link™ virtual channels allow sharing of long physical links in congested areas of the die while maintaining quality-of-service (QoS).
- HBM2 and multichannel memory support
- Meet ISO 26262 ASIL D requirements with optional Resilience Package
- Automate timing closure assistance with optional PIANO Timing Closure Package
- SILICON PROVEN
- FlexNoC is the first commercial NoC interconnect and is shipping in over 2 Billion chips. It is the backbone SoC interconnect used by Huawei / HiSilicon, Samsung, Mobileye, Altera (Intel), and other industry leaders for their most important projects.
- REGULAR TOPOLOGY GENERATION AND EDITING
- FlexNoC AI Package automatically generates mesh, ring and torus interconnect topologies. Unlike black box compiler approaches, SoC architects can edit generated topologies and also optimize each individual network router, if desired.
- Intelligent multicast optimizes the usage of on-chip and off-chip bandwidth by broadcasting data as close to network targets as possible. This allows for more efficient updates of DNN weights, image maps and other multicast data.
- VC-LINK™ VIRTUAL CHANNELS AND SOURCE SYNCHRONOUS COMMUNICATIONS
- For long chip-crossing datapaths and congested wire routing channels.
Video Demo of the FlexNoC AI Package IP Core
Understanding how on-chip interconnect and DDR memory controller configurations impact the system performance, power and cost of multicore SoCs requires deep visibility. Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with the deep, system-level analysis they need to configure and optimize Quality-of-Service (QoS) features earlier in the design cycle.