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USB 3.0 femtoPHY - TSMC 16FFPGL, FFPLL, FFC x1 OTG, North/South Poly Orientation
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FlexNoC Resilience Package IP
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels.
In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.
Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.
In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.
Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.
Features
- Data protection through ECC and parity checking
- Out-of-the-box support for ARM Cortex-R5 and Cortex–R7 Processor Port Checking
- Unit protection by duplication and redundancy
- Similar to dual-core lockstep (DCLS) and often required for ASIL C or D systems as specified in the automotive ISO 26262 standard
- Duplicate unit checkers and fault safety controller
- Built in Self-Test (BIST) for resilience functions
- Data protection by monitoring
- Data packet integrity checkers
- Easy partitioning of any SoC into resilient and non-resilient domains.
Block Diagram of the FlexNoC Resilience Package IP IP Core
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