English
You are here:
Floating-point Divider
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.
Ideal for floating-point pipelines, arithmetic units and processors.
View Floating-point Divider full description to...
- see the entire Floating-point Divider datasheet
- get in contact with Floating-point Divider Supplier
Block Diagram of the Floating-point Divider IP Core
IEEE 754 IP
- Single- and double-precision IEEE-754 floating-point unit
- Single precision, IEEE 754, floating point multiplier
- Single precision, IEEE 754, floating point square root
- 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096
- Single precision floating-point fast speed parametrized multi operands adder
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs