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Floating-point Divider
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.
Ideal for floating-point pipelines, arithmetic units and processors.
Features
- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Trade off latency vs. speed
- FPGA clock rates of 300 MHz+
- Low area footprint
Benefits
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation testbench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
Block Diagram of the Floating-point Divider IP Core
View Floating-point Divider full description to...
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IEEE 754
- Single- and double-precision IEEE-754 floating-point unit
- IEEE 754 Floating Point Coprocessor
- Single precision floating-point fast speed parametrized multi operands adder
- Single precision floating-point parametrized multi operands square sum
- Single precision floating-point 2 cycle's multiplier
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs