English
You are here:
- Silicon IP Catalog >
- Other >
- Arithmetic & Mathematic >
- Adder/Subtractor >
- Floating-Point Adder/Subtractor
Floating Point Megafunctions
Many modern digital signal processing (DSP) systems employ floating-point functionality to achieve the high degree of numeric precision and dynamic range that most applications require. Applications such as radar, sonar, bioscience and molecular science, financial modeling, advanced wireless antenna processing, medical imaging, image analytics and synthesis and precision control are just a few applications that are creating a demand for floating-point capabilities in FPGAs. Furthermore, as FPGAs continue to grow in size and capability, they are becoming the highest performance platform available for any type of floating-point-based algorithm or computation.
Altera provides the largest library of IEEE 754-compliant floating-point megafunctions, and they can all be used in any Altera® device family. Key megafunctions include:
* Addition/subtraction [altfp_add_sub]
* Multiplication [altfp_mult]
* Division [altfp_div]
* Square root [altfp_sqrt]
* Compare [altfp_compare]
* Logarithm [altfp_log]
* Exponential [altfp_exp]
* Inverse [altfp_inv]
* Inverse square root [altfp-inv_sqrt]
* Matrix multiplier [altfp_matrix_mult] (New with v 9.0)
Altera provides the largest library of IEEE 754-compliant floating-point megafunctions, and they can all be used in any Altera® device family. Key megafunctions include:
* Addition/subtraction [altfp_add_sub]
* Multiplication [altfp_mult]
* Division [altfp_div]
* Square root [altfp_sqrt]
* Compare [altfp_compare]
* Logarithm [altfp_log]
* Exponential [altfp_exp]
* Inverse [altfp_inv]
* Inverse square root [altfp-inv_sqrt]
* Matrix multiplier [altfp_matrix_mult] (New with v 9.0)
Features
- Floating-point computation performance is typically a balanced combination of the frequency at which the operators run and the pipeline latency of the operator hardware. This product yields a measure of GFlop performance metric. When designing for maximum GFlop performance in an FPGA, the total number of operators that can be placed in an FPGA is vital. As such, you can parameterize the Altera floating-point megafunctions in many different ways to fine-tune GFlop performance (or, similarly, for other key metrics such as power and area) to meet the application-specific requirements. The configurable features include:
- Single and double precision selection
- Single extended configurable precision
- Operator latency versus area tradeoff
- Reduced functionality
- Optional de-normalized number support
- Reduced rounding accuracy
- Optional indefinite support
- Support for dedicated multiplier circuitry (multiplier only)
- Optional add or subtract-only mode (adder/subtractor only)
View Floating Point Megafunctions full description to...
- see the entire Floating Point Megafunctions datasheet
- get in contact with Floating Point Megafunctions Supplier
DSP
- Tensilica HiFi 5 DSP for AI Speech and Audio Processing
- Software-Compatible DSPs For Radar, Lidar and 5G Applications
- DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications
- Scalable Multi-core Processor
- Multipurpose Hybrid DSP and Controller Architecture Family
- World's most advanced communication DSP, providing cutting-edge performance for multi-Gigabit class connectivity