FortiCrypt AES SX Series IP Core
The core protection mechanism was verified using the rigorous Test Vector Leakage Assessment (TVLA) test. Resistance against attacks was validated analytically and on a physical device. The cores are fully synthesizable and do not require custom cells, memory arrays, or special place & route handling. The AES cores are highly configurable providing a solution for various market segments from resource-constrained to performance-hungry. The configurable security parameter allows for achieving the required balance between cost and protection level. The user can choose a stand-alone cryptographic core or integrated with a register block attached to one of the AMBA AXI or APB busses.
For the ultra-high-bandwidth cores, refer to the FortiCrypt AES-XP product information.
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