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FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz
V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).
At a maximum pixel rate of 112Mhz, LVDS data line speed is 784Mbps, providing a total maximum bandwidth of 3.92Gb/s (490Mbytes per second).
Four (4) instances can provide FullHD @ 120Hz (3DTV)
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).
At a maximum pixel rate of 112Mhz, LVDS data line speed is 784Mbps, providing a total maximum bandwidth of 3.92Gb/s (490Mbytes per second).
Four (4) instances can provide FullHD @ 120Hz (3DTV)
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FPD IP
- LVDS FPD Display Interface Transmitter IP (Silicon Proven in GF 65LPe/ /55LPe)
- LVDS FPD Display Interface Transmitter IP (Silicon Proven in GF 28nm)
- LVDS FPD Display Interface Receiver IP (Silicon Proven in IDM 180nm /150nm)
- FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
- 0.6G-4Gbps V-by-One/LVDS Transmitter PHY IP (Silicon Proven GF 22FDX)
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression