This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).
At a maximum pixel rate of 90Mhz, LVDS data line speed is 630Mbps, providing a total maximum bandwidth of 3.15Gb/s (394Mbytes per second).
- Layout structure based on 1P6M, 1P7M, or 1P8M 0.13um Logic Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 3.15Gbps bandwidth (20 to 90Mhz pixel clock)
- Input clock detector (self reset when missing clock)
- Low bounding pad count
- Spread-spectrum input clock support (can be used in SS systems)
- Core cell area : [contact us]
- Current consumption [contact us] @ 75Mhz
- Built-in power pads with ESD protection.
- Low leakage power-down mode <1uA.
- Four (4) instances support full HDTV @120hz (3DTV)
- Lowest bounding pad count
- Low cost IP
- highly adjustable
- customization for your own design
- Design kit includes :
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- Tapeout kit includes the design kit plus plysical view:
- LVS netlist and report
- DRC/ERC/ESD/ANT report