V-Trans ‘s FPD Link Receiver Macro is based on
National Semiconductor openLDI specification v0.95
dated May 13th 1999 that allow the transfer of digital
display data between a display source and a display
This receiver converts 5 LVDS, (low voltage differential
signaling) data streams, into 30bits (single pixel) CMOS
data plus 5 control signals (VSYNC, HSYNC, DE, and 2
Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 5.95Gb/s (744Mbytes per second).
2 Instances can provide FullHD @ 120Hz data rate !