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MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
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FPGA Evaluation Platforms for RISC-V Processor Cores
This FPGA platform aims to simplify the evaluation of a Codasip low-power (L family) or high-performance (H family) embedded cores. The platform is available to companies with an evaluation agreement. The subsystem is based on AHB and provides a variety of commonly-used peripherals which enable the rapid testing and assessing of a core on an Xilinx-based Digilent Nexys A7 FPGA board.
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Block Diagram of the FPGA Evaluation Platforms for RISC-V Processor Cores
Processor IP
- Real-time detector of zero-day attacks on processor - Cyber Escort Unit
- Real-time Pixel Processor
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-660 DPA & Fault Injection Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
- RISC-V processor - 32 bit, 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline