In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. The Low Density Parity Check (LDPC) codes are powerful, capacity-approaching channel codes and have exceptional error correction capabilities. The algorithm’s high degree of parallelism enables efficient, high-throughput hardware architectures.
The ntLDPCE core implements the LDPC Block Codes (LDPC-BC). These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matri-ces, each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base (block) matrix. The main advantage is that they offer high throughput at low implementation complexity and they are used in many applications and communication standards.
The ntLDPCE core is fully configurable and compliant with various wireless and wireline communication standards including ITU-T G.9960 (G.hn), IEEE 802.16e (WiMAX), IEEE 802.11n/ac (WiFi) etc. Particularly, the core is highly reconfigurable and it is able to support different sub-matrix sizes (Z) of LDPC-BC, that are tailored for specific applications. It also supports varying on the fly code rates. The implementation is flexible, high speed, area optimized and has a simple interface for easy integration in SoC applications.
- Fully configurable, high throughput, highly optimized silicon implementation.
- Supports multiple LDPC coding standards.
- Variable on the fly code rates.
- Supports variable sub-matrix sizes (Z).
- Flexible interface for easy system integration.
- Fully synchronous design, using single clock.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Matlab model.
- Comprehensive technical documentation.
- Technical support.
- Next generation Wired Home: Networking G.9960/G.9961 (G.hn).
- Digital Video Broadcasting: DVB-S2, DVB-S2X, DVB-T2, DVB-C2.
- Deep-space satellite missions (CCSDS).
- WiMax (IEEE 802.16e).
- WiFi (IEEE 802.11n - IEEE 802.11ac).
- WiGig (IEEE 802.11ad).
- WPAN (IEEE 802.15.3c).
- Hard disks.
- 10 Gigabit Ethernet - 10GBASE-T (IEEE 802.3an).
Block Diagram of the Fully Configurable LDPC Encoder IP Core