ntFFT core is a fully configurable solution that performs the FFT and IFFT transform. It is on-the-fly programmable in terms of transform size and type. It supports complex input/output and the results are output in normal order. It exhibits a highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision. The core uses fixed-point 2’s complement arithmetic with internal auto scaling to avoid arithmetic overflow and simplify dynamic range management. The ntFFT IP Core employs a revolutionary parameterized architecture where the user can fine tune the level of data-path parallelism in order to achieve the optimum trade-off between silicon resources and throughput rate. The implementation is portable to various silicon technologies, with a simple interface for easy integration in SoC applications.
- Radix-2 Fast Fourier Transform processor IP Core.
- Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
- Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
- Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
- Tested against Matlab FFT and IFFT functions the ntFFT core produces fixed point numerical results with mean absolute error in range of 1e-4. The core may be parameterized for greater internal fixed point precision to lower the mean absolute error further.
- Final fixed point scaling to avoid precision loss is performed internally.
- Highly programmable design supporting all power of 2 FFT/IFFT transforms in range [8,…,MAX_NFFT], where MAX_NFFT=[8,…,8192]. Support for any power of 2 higher than 8192 is also possible.
- Parameterized architectural parallelism level to meet any target application by tuning an efficient trade-off between utilized resources and maximum throughput rate.
- Overclocked main memory at 2x rate to achieve minimum memory resources utilization.
- Simple yet robust interface for optimum and efficient data flow control.
- Optional AXI4-Stream protocol interface support.
- Synchronous clock design.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
- RMM compliant synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Matlab model.
- Comprehensive technical documentation.
- Technical support.
Block Diagram of the Fully Configurable Radix 2 FFT/IFFT Processor