Fully digital sensor against EM and body biasing fault injections

Features

• f​​ully digital architecture packaged as a standard cell
• totally compliant with any standard cell design flow
• robust detection of EM and body biasing fault injections
• detection of both front-side and back-side EM injections
• EM pulse susceptibility higher than that of standard designs
• detection of fault injection at both rising and falling edges
• permanent check of the internal output signals coherence
• detector size smaller than 50 equivalent NAND2 gates
• silicon proven on several families of advanced FPGA
• successfully evaluated by two security laboratories

Benefits

• High sensitivity
• Standard cell like
• Ultra low power
• Very compact
• ​Easy integration

Deliverables

• GDSII stream and layer map file
• Library Exchange Format (LEF) file
• Circuit Description Language (CDL) netlist
• Liberty Timing File (.lib and .db)
• VHDL behavioral model
• design specification​

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