You are here:
- Fully compliant with USB2.0 specifications as provided by USB Organisation.
- Compliance to Test Suites as provided by USB Organisation.
- Supports High Speed (480 Mbps) Devices.
- Backward Compatible to USB v1.1 and v1.0
- Supports Full Speed (12 Mbps) Devices.
- Supports Low Speed (1.5 Mbps) Devices.
- Generic 8-Bit Microcontroller Interface.
- Includes Packet Assembler, Packet Disassembler and a Protocol Engine in Protocol Layer.
- Supports Bulk, Interrupt and Isochronous type transfers.
- Automatic data retry mechanism.
- Highly intelligent remote wake-up function.
- Support for control transfers by endpoint zero.
- In system Endpoints - 1 In Endpoint, 1 Out Endpoint 1 Control Endpoint.
- IN Endpoint and/or OUT Endpoint may be configured as Bulk or Isochronous or Interrupt Endpoint.
- Endpoint Buffers are Integrated 4Kbytes on chip data buffer.
- Endpoints are 8-Bit wide.
- No Gated Clocks.
- Support for UTMI v1.03 (USB Transceiver Macro Cell Interface).
- Supports 2 Clock Domains; 1 from UTMI and 1 from Microcontroller
- Targeted to Xilinx FPGA
- Clock Frequency: 79.1MHz for FPGA (Standard: 60 MHz)
- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.
- Test Bench. (Environment Variable: Verilog)
full description to...
see the entire
get in contact with