The Graychip Emulation core provides a practical alternative to the Graychip devices that the manufacturer no longer recommends for new designs. It is fully compatible with existing software designed for GC1012B. A functional, rather than pin-for-pin replacement, it is easy to integrate as the design’s new PCB is developed so that it can be connected directly to the same components as the existing design. Thanks to its modern FPGA-based architecture, RFEL’s Graychip Emulation improves on both speed and power consumption over GC1012B. It even offers extra capabilities not available on the original device. RFEL’s Graychip Emulation core stands out as a complete, forward-looking solution for designers looking to breathe new life into ageing Graychip-based systems.
Features
- 110 MS/s sample rate, compared to the 100 MS/s sample rate of the original device.
- Decimation by fractional factors in the range 2 to 16384, covering GC1012B’s options of 2, 4, 8, 16, 32 and 64 and many more besides.
- A tuning range matching or surpassing the 0.1Hz of the original device.
- A 75dB dynamic range to match GC1012B, with improved performance available if requested.
- Gain adjustment in steps finer than the original 0.03dB.
- Complete configuration of the register map by the designer at build time.
- 12-bit output width, or any other width requested, subject to FPGA resource requirements.
- A configurable number of outputs.
- Options for different output formats if desired.
Benefits
- The Graychip Emulation core provides a feature set which not only matches but extends the functionality of GC1012B, including:
- Faithful reproduction of the input/output characteristics of GC1012B.
- Greater flexibility in decimation factors and number of outputs.
- Increased sample rate and dynamic range.
- Finer gain control.
- Larger numbers of outputs and different data formats available on request.
- System architects looking to create the next generation of their Graychip-based products now have a realistic way of upgrading their designs without re-engineering the whole signal processing sub-system.
Block Diagram of the Graychip Emulation core