Artificial intelligence (AI), high-performance computing (HPC), cryptocurrency mining, and graphics applications generate and consume large volumes of data and video and require very high memory bandwidth. The Cadence® Denali® DDR IP is a family of high-speed on-chip interfaces to external memories, with the bandwidth necessary to support these applications.
The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwidth, while supporting extensive value-added features including, but not limited to reliability features. Developed by experienced teams with industry-leading domain expertise and based upon Cadence’s widely proven DDR controller IP, the Controller IP for GDDR6 can provide customers with ease of integration and fast time-to-market.
The Controller IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Cadence Denali® PHY IP for GDDR6 as part of a complete memory subsystem solution that also includes Cadence Verification IP (VIP). The Controller IP is designed to connect seamlessly and work with Cadence or third-party DFI-compliant PHY IP. Developed for and available in alignment with the PHY IP on advanced semiconductor process nodes, the Controller IP is designed to be robust under various traffic loads and to have interoperability with various supplier memory chips.
The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.
- Compatible with GDDR6 devices compliant to JESD250a
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
- Supports in-line ECC
- Priority-per command on Arm® AMBA®3 AXI and low-latency Denali interface
- Single and multi-port host interface options
- QoS features allow command prioritization on Arm AMBA4 AXI interfaces
- Flexible paging policy including auto-precharge-per-command
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging GDDR6 standards
- Clean, readable, synthesizeable Verilog RTL
- Synthesis and STA scripts
- Documentation—integration and user guide, release notes
- Sample verification testbench with integrated BFM and monitors
Block Diagram of the GDDR6 Controller IP Core