GDDR6 interface provides full support for the GDDR6 interface, compatible with standard JESD250, JESD250A and JESD250B specification with version 3.06. Through its GDDR6 compatibility, it provides a simple interface to a wide range of low-cost devices. GDDR6 IIP is proven in FPGA environment. The host interface of the GDDR6 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
- Implemented in Unencrypted Verilog, VHDL and SystemC
- Fully synthesizable
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The GDDR6 interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.