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Compact 32-bit MCU core for deeply embedded applications and accelerator control
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GDDR6 Memory PHY
Designed for performance and power efficiency, the GDDR6 PHY enables big data analytics, crypto mining, ADAS, AI, machine learning, and deep learning.
The Rambus GDDR6 (Graphics Double Data Rate) Memory PHY is designed for the communication to and from high-speed, high-bandwidth GDDR6 SGRAM (Synchronous Graphics Random Access) memory. Originally designed for graphics applications, it is a high-performance memory solution that can be used in a variety of high-performance applications that require large amounts of data computation like artificial intelligence (AI), crypto mining, deep learning, autonomous vehicles, and high-speed networking.
The Rambus GDDR6 PHY is fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin. The interface supports 2 channels, each with 16 bits for a total data width of 32 bits. The Rambus GDDR6 PHY therefore supports a maximum bandwidth of up to 64 GB/s. This PHY is available in advanced FinFET nodes for leading-edge customer integration. The Rambus system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Rambus offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
The Rambus GDDR6 (Graphics Double Data Rate) Memory PHY is designed for the communication to and from high-speed, high-bandwidth GDDR6 SGRAM (Synchronous Graphics Random Access) memory. Originally designed for graphics applications, it is a high-performance memory solution that can be used in a variety of high-performance applications that require large amounts of data computation like artificial intelligence (AI), crypto mining, deep learning, autonomous vehicles, and high-speed networking.
The Rambus GDDR6 PHY is fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin. The interface supports 2 channels, each with 16 bits for a total data width of 32 bits. The Rambus GDDR6 PHY therefore supports a maximum bandwidth of up to 64 GB/s. This PHY is available in advanced FinFET nodes for leading-edge customer integration. The Rambus system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Rambus offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
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Block Diagram of the GDDR6 Memory PHY IP Core
