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GDDR6 PHY - TSMC12FFc
With the advancement of artificial intelligence (AI), deep neural networks (DNN), ADAS, and high-performance computing (HPC), there is an ever-increasing demand for higher memory bandwidth. Along with the large amount of data generated by these applications, the memory sub-system plays a crucial role in the overall performance.
TSS GDDR6 PHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision. The result is ultra low PHY read/write latency between memory controller and the GDDR6 DRAM without sacrificing performance.
The TSS GDDR6 PHY IP, operating at up to 16Gbps data rates in a 32-bit 2-channel configuration, provides a peak memory bandwidth of 64GB/s, with the following technical features:
* Continuous IO impedance and timing phase updates with no traffic interruption
* Support for x16, x8, and PC modes
* DFI 4.0 interface to memory controller with extension for GDDR6 support
* Wide operating frequency range with low frequency RDQS mode support
* PHY-independent initialization of DRAM and training – no memory controller involved
* TX pre-emphasis and de-emphasis, RX continuous-time linear equalization (CTLE) and decision-feedback equalization(DFE) improves WRITE and READ eye margins
* Multiple frequency set points (FSP) enables rapid frequency change
* Ultra low READ/WRITE latency with programmable PHY boundary timing
TSS understands that aside from performance and power, the implementation requirement at the system level such as package stack up layer count and PCB layer count are also crucial factors to consider at the product level. This is why the TSS team designed the GDDR6 PHY with the lowest system level implementation cost in mind, allowing cost sensitive applications to reap the benefits of this blazing fast memory standard.
The TSS GDDR6 PHY is available and has been silicon proven in TSMC N12 process technology.
TSS GDDR6 PHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision. The result is ultra low PHY read/write latency between memory controller and the GDDR6 DRAM without sacrificing performance.
The TSS GDDR6 PHY IP, operating at up to 16Gbps data rates in a 32-bit 2-channel configuration, provides a peak memory bandwidth of 64GB/s, with the following technical features:
* Continuous IO impedance and timing phase updates with no traffic interruption
* Support for x16, x8, and PC modes
* DFI 4.0 interface to memory controller with extension for GDDR6 support
* Wide operating frequency range with low frequency RDQS mode support
* PHY-independent initialization of DRAM and training – no memory controller involved
* TX pre-emphasis and de-emphasis, RX continuous-time linear equalization (CTLE) and decision-feedback equalization(DFE) improves WRITE and READ eye margins
* Multiple frequency set points (FSP) enables rapid frequency change
* Ultra low READ/WRITE latency with programmable PHY boundary timing
TSS understands that aside from performance and power, the implementation requirement at the system level such as package stack up layer count and PCB layer count are also crucial factors to consider at the product level. This is why the TSS team designed the GDDR6 PHY with the lowest system level implementation cost in mind, allowing cost sensitive applications to reap the benefits of this blazing fast memory standard.
The TSS GDDR6 PHY is available and has been silicon proven in TSMC N12 process technology.
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Block Diagram of the GDDR6 PHY - TSMC12FFc IP Core
