PLDA Gen-Z Controller IP Core is a highly scalable and configurable semiconductor IP core compliant to the Gen-Z Core Specification 1.0a and Gen-Z PHY Specification 0.9a, and suitable for both media-side and host-side implementation. The controller integrates multiple requesters, mutiple responders, and multiple Zlink, interconnected together through a switch core. The architecture allows for each of these functional modules to be reused independently for even greater scalability. At the user interface level, the Gen-Z Controller IP offers an ultra-low latency, variable width native interface, or a standardized AMBA 4 AXI (AXI4) interface. The Gen-Z controller can optionally be configured to implement PLDA vDMA many-channel DMA engine as well as a ZMMU for supporting complex address translation and memory management. At the PHY level, PLDA is working with our PHY Partners to offer a complete, pre-integrated and validated interfacing solution for Gen-Z on various process nodes and foundries, as well as on leading edge FPGA devices.
PLDA Gen-Z Controller IP is co-developed with Gen-Z Consortium founding member HPE.