Gen2 DDR multiPHY in SMIC (28nm)
A key component of the DesignWare Gen 2 DDR multiPHY is the extensive in-system data training/calibration capability that is used to maximize the overall timing budget and improve system reliability. The DesignWare Gen 2 DDR multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The Gen 2 DDR multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs.
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SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.