The Gen3 PCIe to AHB Bridge is a highly flexible and configurable IP with a PCI Express* interface on one side and an AMBA AHB interface on the system side. The Bridge has been architectured to interface with a PCI Express* controller used as an end-point or root-complex type devices. The Gen3 PCIe to AHB Bridge uses high speed multi-channel DMA controllers to match the bandwidth requirements of the PCIe Gen3 solution.
The Gen3 PCIe to AHB Bridge is part of the PCI-Express (GPEX) family of IP solutions which includes Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH), GPEX-AXI Bridge (GPEX-AXI) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. The solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
The Gen3 PCIe to AHB Bridge leverages years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
- Compliant to PCI Express base specification version 3.0, Oct 2011 Errata for 3.0 and backward compatible with PCI Express versions 2.0 and 1
- AMBA AHB 2.0 compliant
- Full and Lite mode operation supported
- AMBA PIO operation with configurable number of AHB Slaves supported
- PCIE PIO operation with configurable number of AHB Masters supported
- Multi-channel DMA transfers supported
- Register based and descriptor based modes of DMA supported
- Optional configurable number of Read and write DMAs supported
- Verified with leading AHB VIP
- Superior architecture-high performance, low latency and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- PC’s workstations and servers
- Networking and communications
- Switches and routers
Block Diagram of the Gen3 PCIe to AHB Bridge