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PCI Express Gen1/Gen2/Gen3 Root Complex Controller with SRIOV Support
The PCI Express Root Complex Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.
The PCI Express Root Complex Controller is part of the PCI-Express (GPEX) family of IP solutions which includes Endpoint (GPEX-EP), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
The PCI Express Root Complex Controller leverages years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
The PCI Express Root Complex Controller is part of the PCI-Express (GPEX) family of IP solutions which includes Endpoint (GPEX-EP), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
The PCI Express Root Complex Controller leverages years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
Features
- Compliant to PCI Express base specification 5.0 (32 Gbps per lane) and backward compatible with PCI Express versions 4.0, 3.1, 2.0 and 1.1
- Supports configurable number of PFs and VFs for SR-IOV
- Architected for high link utilization and low latency
- Efficient receive and transmit-retry buffering scheme
- Completely handles PCI-Express ordering rules
- Implements flow control logic in both directions
- Packet oriented user logic interface
- Supports PIPE 5.0 Compliant PHYs
- Flexible lane ordering and support for lane reversal
- Supports separate RefClk independent SSC architecture-SRIS
- L1 PM Sub-states (Low Power States) with CLKREQ#
- Supports Bifurcation
Benefits
- Configurable Options
- Maximum Link Width (x1, x2, x4, x8, x16)
- Maximum TLP data payload size supported (128B to 4KB)
- Data Path Widths (32, 64, 128, 256 and 512 bit)
- 8-bit/ 16-bit/ 32-bit/ 64 bit PIPE interface
- Transmit Retry / Receive Buffer size
- Number of Virtual Channels
- Inclusion of specific sublayers etc.
- ASPM L1 / Wake support, Auxiliary power support
- Hot plug support
- L1 PM Substate Support
- Design Attributes
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
- Multiple loop backs for debug
Deliverables
- Verilog RTL Code
- UVM based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
Applications
- PC’s workstations and servers
- Storage
- Networking and communications
- General purpose system chip interconnect for any compute platform
Block Diagram of the PCI Express Gen1/Gen2/Gen3 Root Complex Controller with SRIOV Support
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PCI Express IP
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- 1-32Gbps PCI-Express Gen1 - Gen5 PHY