Perceptia’s DeepSub™ pPLL02F is a family of all purpose all digital PLLs featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as a clock source for moderate speed microprocessor blocks and other logic.
Perceptia’s second generation pPLL02F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL02F is very small (< 0.005 sq mm) and low power (< 1.7mW in GF22FDX). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL02F has an integrated power supply regulator which allows multiple instances of PLL02F to share common power supplies. Alternatively instances of pPLL02F can share supplies with the blocks that use its output clock.
pPLL02F integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL02F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL02F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
- Low jitter, suitable for many clocking applications
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 2GHz
- Reference clock from 5MHz to 500MHz
- Second-generation digital PLL architecture, providing integer and fractional multiplication
- Primary PLL output running at the main DCO frequency for lowest noise clocking
- Two further PLL outputs via separate postscalers
- Post-scalers programmable from 1 to 2,040
- Lock-detect output
- Can generate a spread-spectrum clock from a clean reference
- Oscillator output duty cycle better than 48 / 52%
- Highly testable using industry standard flows
- ATPG vectors provided
- Specification of functional tests to supplement ATPG testing
- Industrial operating conditions
- Low jitter (< 18ps RMS)
- Small size (< 0.005 sq mm)
- Low Power (< 1.7mW in GF22FDX)
- Support for multi-PLL systems
- Easy integration
- Fractional Multiplication
- Detailed Verilog behavioral model
- Timing models
- LEF5.6 abstract for floor planning/chip assembly
- Integration Guide
- DFT Guide
- Integration support
- Characterization report
- GDSII layout macrocell
- CDL netlist for LVS
- DRC, LVS and SI verification reports
- Netlist model with accompanying documentation – allowing integration of the module in scan chains
- Moderate speed digital systems
- General-purpose PLL
Block Diagram of the General Purpose Fractional-N PLLs IP Core