CoreGPIO is an APB bus peripheral that provides up to 32 inputs and 32 outputs for general purpose use. The core is intended for use with the Microsemi soft processors: Cortex-M1, Core8051s, and CoreABC. There is a single register at offset 0x00 and aliased throughout the slot. Writing to this register writes 32 bits to the outputs. Reading from this register reads the state of the inputs.
It is not required that all inputs and outputs be used. The user need only connect to those inputs or outputs which are actually used.