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General purpose microprocessor incorporating a high performance L1 cache controller and virtual memory management support for high performance embedded system applications
The MIPS32® M5150 core from Imagination Technologies is a member of the MIPS32 M5150 processor core family. It is fully confgurable/synthesizable, ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information-management markets, enabling new tailored solutions for embedded applications.
The M5150 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5150 core is an enhancement of the microAptiv™ UP, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5150 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5150 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions
The M5150 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5150 core is an enhancement of the microAptiv™ UP, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5150 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5150 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions
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