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MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave
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General purpose microprocessor incorporating a high performance L1 cache controller and virtual memory management support for high performance embedded system applications
The MIPS32® M5150 core from Imagination Technologies is a member of the MIPS32 M5150 processor core family. It is fully confgurable/synthesizable, ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information-management markets, enabling new tailored solutions for embedded applications.
The M5150 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5150 core is an enhancement of the microAptiv™ UP, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5150 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5150 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions
The M5150 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5150 core is an enhancement of the microAptiv™ UP, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5150 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5150 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions
Features
- Architecture
- MIPS32 Release 5 Architecture
- microMIPS ISA Enhanced code compression ISA of combined 16- and 32-bit instructions
- Supports all existing MIPS32 instructions; adds new 16- and 32-bit instructions
- Enables up to 30% code size reduction relative to 32-bit only code
- Hardware Virtualization
- Create multiple execution environments (Guest) isolated from each other, operating at kernel privilege level
- Hypervisor/Secure Monitor (Root) manages access rights for each Guest
- Supports Type 1 and Type II hypervisors
- Supports up to 7 Guests, each supplied a unique ID; Guest OS runs un-modified
- 7 new instructions facilitate Root-to-Guest communication
- Supports multiple Memory Management Unit options for optimum area vs. functionality
- M5100 – FMT + Root Protection Unit
- M5150 – Guest TLB + Root TLB
- M5150 – Guest TLB + Root Protection Unit
- Allows sharing of resources (memory, DSP, FPU etc.) between Guests
- DSP Module r2
- Dedicated pipeline, operates in parallel with core integer pipeline
- Implements over 150 instructions, including 70 SIMD and 38 Multiply/MAC instructions
- Enhanced Multiply & Divide Unit
- Single cycle throughput multiply and MAC operations
- Supports 32x32, 16x16, dual 16x16, dual 8x8, dual 8x16
- Supports up to 4 Accumulators
- Floating Point Unit (FPU)
- Single and double precision IEEE 754 compliant FPU
- Supports IEEE-754 2008 Nan and ABS instructions
- Dedicated 7-stage pipeline, operating in parallel with core integer pipeline
- Most instructions execute with 1 cycle throughput and 4 cycle latency
- Executes 1:1 Core:FPU clock ratio
- Supports both MIPS32 and microMIPS instructions
- Anti-Tamper
- Injection of random pipeline stalls
- Cache/SPRAM address and data scrambling
- 2 pseudo random number generators for use by the user software and core logic
- Memory Controller
- M5150 – L1 cache controller for Instruction and Data sizes up to 64KB, 4-way set associative
- M5100 – 32-bit address and data SRAM interface, separate or unified instruction and data interface
- Bus Interface Unit
- AMBA 3 AHB
- EJTAG Debug & Trace
- Secure debug feature – prevents streaming instructions through the EJTAG port
- Supports enhanced iFlowtrace™ with additional event trace modes
- Simple/Complex instruction and data breakpoint support – 2I/1D, 4I/2D, 6I/2D, 8I/4D
- Support for 2 Performance Counters with multiple event type options
- Instruction and data address sampling: zero overhead, qualified read/write
- Support for 2-wire cJTAG debug interface
- Power Management
- Incorporates extensive fine-grain clock gating
- Implements a Power Down mode initiated by a WAIT instruction
- Expandability
- Optional co-processor (COP2) and CorExtend™ / User Defined Instruction (UDI) interfaces
Benefits
- Standard architecture, proven in millions of SoC designs
- High-performance, area- and energy- efficient architecture: performance requirement achieved at lower frequency and smaller size than the competition
- Hardware virtualization – supports multiple software environments running independently, securely, efficiently and in complete isolation to each other
- Available in microcontroller and embedded processor versions for use in a wide range of operating environments
- Combined MCU and DSP technology for cost-effective signal processing
- Flexibility and scalability – single design to cover a broad range of applications
- FPU to accelerate real-time control in industrial, automotive and digital consumer applications
- Broad software and ecosystem support, and mature toolchain
- Available as synthesizable IP for implementation in any process node, with standard cells and memories
Applications
- Industrial control and automation
- Internet of Things (IoT), Machine to Machine (M2M)
- Wearables
- Home appliances, digital consumer products
- Automotive
- Cloud computing
- Network communications
- Storage
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