English
You are here:
General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications
The MIPS32® M5100 core from Imagination Technologies is a member of the MIPS32 M5100 processor core family. It is fully configurable/synthesizable, especially well-suited for microcontrollers and embedded applications that have real-time requirements with a high level of performance efficiency and security requirements.
The M5100 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5100 core is an enhancement of the microAptiv™ UC, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, a reference design of an optimized interface for flash memory and built-in native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5100 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5100 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions.
The M5100 core implements the MIPS® Architecture Release-5 (“R5” incorporating enhanced functionality for next generation MIPS-Based™ products) in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provides a significant reduction in code size with a performance equivalent to MIPS32. The M5100 core is an enhancement of the microAptiv™ UC, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, a reference design of an optimized interface for flash memory and built-in native AMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, security, debug, and profiling features. In addition, the M5100 core includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment.
The M5100 core has an option to include the MIPS Architecture DSP Module Revision 2 that executes digital signal processing capabilities, with support for a number of powerful data processing operations. An optional IEEE 754 compliant Floating-Point Unit (FPU) provides both single and double precision instructions.
View General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications full description to...
- see the entire General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications datasheet
- get in contact with General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications Supplier
Block Diagram of the General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications
