MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
GLink Multi-Slice PCS
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
View GLink Multi-Slice PCS full description to...
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