The S3TXBIAST55ULP circuit has been designed to reduce time to market, risk and cost in the development of analog front-ends. A range of supporting IP blocks such as PLL's, clock buffers, amplifiers, Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters are also available.
The S3TXBIAST55ULP has been implemented on standard 65nm LP basic logic process. However, it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
The Bandgap circuit is a standard implementation using an array of matched PNP transistors to generate the PTAT (Proportional To
Absolute Temperature) term.
The Bandgap voltage is used to create accurate bias currents. These bias currents are generated with an external resistor and whereby this resistor can adjust the output full-scale current.
The S3TXBIAST55ULP also generates currents using internal resistor which can be used to generate voltage reference assuming matched resistors are used.
- 55nm TSMC ULP eFlash Process, 6 Metals Used
- 2.5V and 1.2V Supplies
- Accurate 0.8V Bandgap Reference
- Tolerance of Bandgap Voltage < ±3.5%
- Power consumption
- Active mode:5.0mW
- Power down: 0.5uW
- Compact Die Area:0.072mm2
- The S3TXBIAST55ULP is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Reference Generation
- Current & Voltage Regulation
- General Mixed Signal Products
Block Diagram of the Global biasing block IP Core