Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 12nm FinFET process nodes.
Arasan's D-PHY Global Foundry 12nm IP is compliant with MIPI D-PHY(SM) v1.2 Spec and is developed on its 2nd generation D-PHY silicon-proven IP to reduce risk while the design is optimized to leverage the GF 12nm technology node for the reduction in area and power compared to our previous designs.
Arasan’s MIPI D-PHY(SM) for GF 12nm is seamlessly integrated with Arasan's own MIPI CSI Tx, CSI Rx, DSI Tx, and DSI Rx as part of its Total MIPI Imaging and Display IP Solution.
Arasan’s MIPI D-PHY(SM) for GF 12nm supports speeds of up to 2.5 Gbps for SoC designs.
The Arasan’s GF 12nm MIPI D-PHY Analog Transceiver IP Core is fully compliant with the D-PHY v1.2 specification.
It is a universal PHY that can be configured as a transmitter, receiver, or transceiver.
Arasan’s GF 12nm D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.
Arasan’s GF 12nm D-PHY provides a point-to-point connection between 0host and device that complies with a relevant MIPI® standard. A typical configuration consists of a clock lane and 1-4 data lanes. The host is primarily the source of data, and the device is usually the sink of data. The D-PHY lanes can be configured for unidirectional or bidirectional lane operation, originating at the host, and terminating at the device. It can be configured to operate as a master or as a slave. The D-PHY link supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. In HS mode, the low swing differential signal can support data transfers.
Arasan’s GF 12nm D-PHY Analog Transceiver IP core implements the PPI interface recommended by the MIPI® working groups to easily interface to the required protocols.