This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [5:0] and DN [10:0] to different values according to different FREF, CLK will be locked at the multiples of input frequency.CLKO is CLK divided by DP[2:0].
- Process: GF 22nm FDSOI 0.8V/1.8V CMOS process
- Supply voltage: 1.62V<=AVDD<=1.98V, 0.72V<=DVDD(AVDD2)<=0.88V
- Mos device type: nfet, pfet, egnfet, egpfet
- Operating current: AVDD<1.2mA(1GHz) AVDD<4.8mA(3.2GHz)
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
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