This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications. It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation. The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module. The encoder module computes 16 parity bytes and appends them on the 239 byte information block. The decoder receives the 255 bytes codeword, locates and corrects up to 8 byte errors being introduced in the transmission channel.
- Fully compliant with the ITU-T G.984 (GPON), ITU-T G.983 (BPON) and ITU-T G.709 recommendations.
- Supports ASIC and FPGA implementation technologies.
- Single edge, fully synchronous design.
- Area efficient design.
- Symbol rate clock.
- Supports both streaming of data and gaps between codeword bytes.
- Calculates the number of erroneous bytes.
- Generates a status signal indicating error locations.
- Determines the location and magnitude of the erroneous bytes.
- Corrects up to 8 erroneous bytes.
- Detects uncorrectable codewords.
- Predictable low decoder latency.
- Verilog Source Code
- Test Bench
- Sample Syntheis scripts