The SDXC Controller IP Core supports both SDXC and UHS-I. The SDXC Controller can be embedded for use in FPGA or ASIC.
- Very compact and high-performance image transfer IP core specialized for Altera's FPGA
- Multiple color formats (RGBX 8888, RGBA 8888, RGB 565) supported.
- In addition to transferring the entire area of the image, transferring the rectangular area supported.
- Three types of image synthesis supported. Alpha blending, additive blending, and overwrite blending.
- Alpha blending in pixel units supported.
- Image rotation (180° · V flip · H flip only).
- Enlarging/shrinking the image (bilinear, nearest neighbor).
- Supported pixel size: MAX 2,048 * 2,048 pixel
- Required Logic Elements: 5,500 LE (Reference value) / 2,400 ALMs (Reference value)
- Required Memory: 262,432bit
- Required DSP blocks: 38
- Bus specification: Avalon MM (32bit)
- RTL (Encrypted)
- API specification
Block Diagram of the SDXC Controller IP Core