GSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon GSMC 0.13um LP Process Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, 6 or 7 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
View GSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler full description to...
- see the entire GSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler datasheet
- get in contact with GSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler Supplier