The GSMC18_PLL_01 is developed as a macro cell for clock generation. It can generate a stable high-speed clock from a slower clock signal. The output frequency is adjustable and can be up to 400MHz. The GSMC18_PLL_01 integrates a phase frequency detector (PFD), a low pass filter (LPF), a voltage controlled oscillator (VCO) and other associated supporting circuitry. All fundamental building blocks as well as fully programmable dividers are integrated in the core. It is useful for click multiplication of stable crystal oscillator sources and for de-skew clock signals.
- Technology: GSMC18_PLL_01 is a 1P3M layout structure based on GSMC 0.18um 1P6M 1.8V logic process.
- Single power supply: 1.8V
- Input clock frequency range from 2MHZ to 50MHZ.
- Output clock frequency range from 25MHZ to 400MHZ.
- Low jitter