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Voltage Domain Interfacing Cells for use between power domains using core transistors.
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GSMC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.25um High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.25um Logic 1P5M Salicide 2.5/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
Features
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
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SRAM
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Single Port, Ultra High Speed, GF 22FDX, SRAM Memory Compiler
- 32-bit SRAM/PROM Controller