GSMC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
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SRAM IP
- Memory (SRAM, DDR, NVM) encryption solution
- Complete Neural Processor for Edge AI
- Intrinsic ID Zign® 100 - Software implementation of SRAM PUF
- Intrinsic ID Zign® 200 - Software implementation of SRAM PUF with symmetric cryptography
- Intrinsic ID Zign® 300 - Software implementation of SRAM PUF with symmetric & asymmetric cryptography + PKI
- 32-bit SRAM/PROM Controller