GZIP compression/de-compression standard had become in-practice the standard for lossless data compression. GZIP compression is very popular in many applications that benefit out of the smaller data size, but are unable to lose information (in contrast to graphic applications that use lossy compression methods, such as Jpeg & Mpeg). Examples for such applications:
- Data storage backup devices,
- HTTP web servers,
- Point to point or point to multipoint communications.
- Synthesizable Verilog soft core suitable for FPGA and ASIC implementations.
- RFC1951 (Deflate) and RFC1952 (GZIP) compliance
- Fully Pipelined implementation for maximum performance
- Streaming data interface which enables maximum performance and integration flexibility.
- Optional PCI-X or AMBA I/F.
- Configurable Lempel-Ziv history buffer size (Can save memory size when decompressing blocks that were compressed with a core with a smaller LZ buffer size).
- Configurable Internal data buffer size.
- Very small resource usage.
- Throughput of 1 output byte per clock cycle (decompressed data)
- 36 clock cycles for static Huffman
- 420 clock cycles for dynamic Huffman
- No delay between subsequent files.
- Compression speed (single core):
- ASIC (TSMC 40nm lp): 320MHz gives a sustained compression speed of 2.5 Gbps.
- FPGA: 100MHz on Altera Stratix3 gives a sustained compression speed of 0.8 Gbps.
- Parallel instantiation of several cores is applicable for performance increase.
- Synthesizable Verilog HDL
- Verilog test-bench and test-suite (with Perl script)
- Available option – FPGA demo
Block Diagram of the GUNZIP HW Accelerator IP Core