English
You are here:
GW28-125-USR SerDes
The Glasswing SerDes family is a programmable IP designed and optimized for in-‐package applications. Glasswing provides high system bandwidth with low power consumption through the use of 5b6w Chord™ signaling and employs a forwarded clock architecture. The Glasswing IP may be deployed in multiple instances to provide efFicient extended interfaces.
The GW28-‐125-‐USR SerDes is a hard IP SerDes solution that provides a high throughput for short reach interposer and multi-‐chip-‐module applications such as chip-‐to-‐chip, processor or switch to memory, and in-‐ package interfaces. Typical supported applications will deliver 25GBaud over channels of 5mm to 25mm with insertion losses in the range 3dB to 6dB at Nyquist.
The GW28-‐125-‐USR achieves low power through coding, efFicient circuitry, simple clocking and equalization schemes.
The GW28-‐125-‐USR SerDes is a hard IP SerDes solution that provides a high throughput for short reach interposer and multi-‐chip-‐module applications such as chip-‐to-‐chip, processor or switch to memory, and in-‐ package interfaces. Typical supported applications will deliver 25GBaud over channels of 5mm to 25mm with insertion losses in the range 3dB to 6dB at Nyquist.
The GW28-‐125-‐USR achieves low power through coding, efFicient circuitry, simple clocking and equalization schemes.
Features
- Five 32 bit Rx and Tx parallel busses.
- Operates as a single 6-‐wire 5b6w SerDes
- 62.5Gb/s to 125Gb/s over 6 wires.
- 6 data and 2 forwarded clock wires in each direction, data is 5b6w encoded.
- Supporting common block hard IP with PLL and references.
- DC coupled link requiring no data coding or scrambling.
- Internal Tx to Rx loopback.
- Programmable Tx swing; maximum 300mV single-‐ ended.
- CTLE Rx equalization.
- Clock data aligner (CDA).
- Programmable Rx CDA coefFicients.
- EyeScope (destructive).
- Rate variable through PLL control.
- Pin-‐order reversal.
- Rx bit-‐slipping for word alignment.
- PRBS31 pattern Tx generation and Rx veriFication, plus user deFined pattern.
- DFT: at-‐speed BIST of analog plus stuck-‐at scan of slow digital circuitry.
- JTAG boundary scan (8 wires each direction, 1149.1).
- Supports JTAG boundary scan (1149.1) and scan test modes.
- Analog test port.
- ATPG support.
- APB (ARM Peripheral Bus) interface for easy programming and integration.
- Compliant to proposed JEDEC JC-‐16 Multiwire SpeciFication.
Benefits
- 40% higher throughput over conventional SerDes at the same baud rate over the same number of pins/ wires.
- Enables 2.5D integration through high pin-‐efFiciency and low power.
- FOM 444Gbps/mm bidirectional data as 4TxRx.
- Excellent signal integrity.
- Has differential-‐like EMI performance.
Deliverables
- Data sheet and application notes.
- Channel compliance specification.
- Standard Integration Views: GDS, LEF, verilog, .lib.
- Outline silicon test program.
- Evaluation Module available.
Applications
- Short reach multi‐chip modules:
- Packaging of dies with dissimilar semiconductor processes.
- Packaging of smaller dies to increase yield.
- High throughput data interfaces:
- Processor or switch to wide, high bandwidth memory.
- Efficient interface to off‐board SerDes.
- Efficient interface to optics engines.
- Switch to switch links.
Block Diagram of the GW28-125-USR SerDes IP Core
View GW28-125-USR SerDes full description to...
- see the entire GW28-125-USR SerDes datasheet
- get in contact with GW28-125-USR SerDes Supplier