The GZIP-RD-XDMA is a reference design for a PCIe data compression and decompression acceleration card using the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.
The accelerator is highly efficient and can compress data at rates exceeding 80 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.
The reference design uses Xilinx® DMA for PCIe subsystem (XDMA) and can be mapped on PCIe boards hosting 7-series, UltraScale™ or UltraScale+™ devices. The following table summarizes available off-the-shelf compression-only configurations for Xilinx FPGA boards:
The accelerator’s compression engines, the ZipAccel-C and ZipAccel-D IP cores, are highly configurable and can be tuned to meet different application requirements with respect to silicon resources utilization, compression efficiency, and throughput. CAST will work with you to define the cores’ configuration that meets your application requirements.
The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application.
Deliverables include the firmware (FPGA programming file), software (drivers & sample application), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.
For more information please contact CAST sales.