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90nm OTP Non Volatile Memory for Standard CMOS Logic Process
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H.264 4K Decoder - Supports 4KP60, 4:2:2, 10Bits
The H.264 Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
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Block Diagram of the H.264 4K Decoder - Supports 4KP60, 4:2:2, 10Bits
H.264 IP
- Enhanced Multi-Format Encoder Supporting AV1
- Up To 5 MPixel Multi-Format Encoder
- 1080p60 Multi-Format Decoder IP
- 4K/8K Scalable Multi-Format Video Decoding IP Core
- Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
- H.264 Baseline Encoder with compressed reference frame store