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UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
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H.264 4K Decoder - Supports 4KP60, 4:2:2, 10Bits
The H.264 Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
Features
- Standard: H.264/MPEG-4 Part 10 (ISO/IEC 14496-10 & ITU-T H.264)
- Profiles: Constrained Baseline, Main & High profles
- Video Resolutions: Up to 4096 x 2160
- Frame Rate: Up to 60 fps
- Bit rate: CABAC Bitrate: Up to 160 Mbps
- CAVLC Bitrate: Up to 320 Mbps
- Chroma Format: Monochrome, 4:2:0 & 4:2:2
- Precision: Bit depths from 8 to 10. Scalable to 12
- Input Format: Elementary or Transport stream
- Output Format: Decoded pictures in frame buffer. Optional serial output
- with embedded sync information
- Latency: Ultra low latency of 10 ms
- Codec Flavors: AVC – Ultra, XAVC 4K, XAVC 4K Intra
- FPGA: Xilinx Kintex Ultrascale
Benefits
- Fully standards compliant - tested with ITU-T & other industry standard test suites.
- Robust error handling, resilience & concealment.
- Processes metadata related to closed captions, AFD & picture timing.
- Seamless switching between streams encoded with different settings including different resolutions, chroma formats and bit depths.
- Extensive options to customize the source code via use of parameters
- Single chip solution with no processor requirement
- Supports progressive and interlaced formats
- Supports both CABAC and CAVLC Entropy coding
- Easy to integrate and hence faster time-to-market
Deliverables
- Source Code or Netlist
- Simulation Model
- Hardware Test Platform
- Build Scripts
- Test Reports
- User Manual
- Design Documentation
- Constraint Files
- Test Benches
- Support for one year
Applications
- Broadcast
- Video Contribution & Distribution decoders
- Multi-format digital receivers (IRDs)
- Video / Play-out Servers
- High End Consumer Electronics
- Test & Measurement Equipment’s
- Aerospace & defense
- Medical
Block Diagram of the H.264 4K Decoder - Supports 4KP60, 4:2:2, 10Bits
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