Our FPGA core is highly optimized and 80% SMALLER AND FASTER THAN THE COMPETITION WITH ⟨ 1ms LATENCY @ 1080p30!
It is capable of being synthesized in many FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 95Mhz. Typical clock rate in a Xilinx Zynq 7020 is 95MHz. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.
- 1.5 clocks/pixel processing rate Fully compatible with the ITU-T H.264 specification Available with bus widths from 8-12 to handle deeper pixel depths (Pre-compiled for Binary license.) Supports resolutions up to 4096 x 4096 (can be expanded with additional cores) Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios Generates I and P frames Variable Bit Rate (VBR) and Constant Bit Rate (CBR) Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution Entropy Encoding: CAVLC Support for intra 4 x 4 DC prediction Support for Single or Multiple slices via firmware control Supports YUV 4:2:0 video input Fully synchronous design Available as FPGA specific netlist Custom versions available
- Recent Enhanced Features
- New improved AXI wrapper to simplify integration of core AXI stream for video input and compressed output Latency reduced from 1 frame to less than 1ms for a 1080p30 video stream LOWEST LATENCY IN THE INDUSTRY! Others quote low latency but limit it to I frame only. Our core is low latency and supports I and P frames! Significant reduction in Block RAM requirements for external raster to macroblock reordering
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