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[3495tq-lp] 12-bit, 250MSPS, 1.2V Wideband Pipeline IQ-ADC with 2.5V Input Buffer in TSMC 40LP
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H.264 Encoder High Profile (8K on Zynq/Arria)
The H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. Two encoder variants are available to meet the different targets of features, resource usage, and compression:
• H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression.
• H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression
• H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression.
• H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression
Features
- Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.
- EXTREME SPEED, providing a constant throughput of 5.2 pixels encoded per clock cycle.
- Achieves 8K30 on mid-range Zynq-7030 and Arria 10 FPGAs
- Achieves UltraHD 4K on low-end and low-cost Spartan/Cyclone FPGAs
- Realtime configurable VBR/CBR mode (Variable/Constant Bit Rate) automatically controls all H.264 parameters.
- Very low latency (just 16 lines' time).
- High 4:4:4 Predictive Profile (H264E-P) and CAVLC 4:4:4 Intra Profile (H264E-I and H264E-P).
- Highest level (5.2) of resolutions and frames per second allowed by H.264 standard attained at just 102 MHz (most low-range FPGAs).
- Preserves full color fidelity with color subsampling 4:4:4.
- Selectable number of predicted frames (P) per keyframe (I) on H264E-P.
- Output in Byte stream format (raw .264) for easier encapsulation.
- (H264E-P) Full reconstructed video preview output.
- (H264E-I) Optional pseudo-reconstructed video preview output.
- Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
- Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
- Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
- Optional optimized pixel input mode to boost shared memory efficiency.
Deliverables
- Technical support via email
- IP Core Datasheet
- Xilinx Vivado drag'n'drop instance
- Altera Qsys drag'n'drop instance
- Linux driver for embedded setups
- Example SW control application
Block Diagram of the H.264 Encoder High Profile (8K on Zynq/Arria)
Video Demo of the H.264 Encoder High Profile (8K on Zynq/Arria)
This is the most "interactive demo", with which you can encode your own PC/video-player (attached to DVI input) and see the resulting H264 encoded + decoded stream on the DVI video output (a screen) in realtime. It also allows uploading encoded videos to a PC.
It includes a small Windows app that allows to remotely control and monitor the encoding, a really visual way to evaluate the compression and quality.
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H.264 Encoder
- Lightweight JPEG, H.264/AVC, H.265/HEVC and VP9 Encoder
- JPEG, H.264/AVC, H.265/HEVC (SHVC) and VP9 Encoder
- HEVC + H.264 Codec IP Single Core for 4Kp60
- H.264 High Profiles Encoder - High 10, High 4:2:2 and High 4:4:4 (12 bit 4:2:2 or 4:2:0) Profiles
- CODA7L - H.264 HP, VC-1 AP, MPEG-4 ASP, MPEG-2 MP, RV8/9/10, VP8, AVS up to 1080p 30fps for decoder and H.264 BP, MPEG-4 SP, H.263 P3 up to 1080p for encoder
- H.264 Baseline Encoder with compressed reference frame store
