English
You are here:
H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits
VYUsync’s H.264 1080p60, 4:2:2, 10-bit Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. The leading broadcast companies have incorporated VYUsync’s H.264 Decoder IP in their end products and more than 100,000 products have been shipped. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The Decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of the end users.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The Decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of the end users.
Features
- Standard: H.264/MPEG-4 Part 10 (ISO/IEC 14496-10 & ITU-T H.264)
- Profiles: Constrained Baseline, Main & High profiles
- Video Resolutions: Up to 1920 x 1080
- Frame Rate: Up to 60 fps
- Bit rate: CABAC Bitrate: 40 Mbps. Scalable to 80 Mbps
- CAVLC Bitrate: 80 Mbps. Scalable to 160 Mbps
- Chroma Format: Monochrome, 4:2:0 & 4:2:2
- Precision: Bit depths from 8 to 10
- Input Format: Elementary or Transport stream
- Output Format: Decoded pictures in frame buffer. Optional serial output
- with embedded sync information
- Latency: Ultra low latency of 10 ms
- Codec Flavors: AVC – Ultra, H.264 4K, XAVC
- FPGA: Xilinx Ultrascale, 7-Series and 6-Series FPGAs
- Altera devices are also supported. Contact us for the information.
Benefits
- Fully standards compliant - tested with ITU-T & other industry standard test suites
- Robust error handling, resilience & concealment
- Processes metadata related to closed captions, AFD & picture timing
- Seamless switching between streams encoded with different settings including different resolutions, chroma formats and bit depths
- Extensive options to customize the source code via use of parameters
- Single chip solution with no processor requirement
- Supports progressive and interlaced formats
- Supports both CABAC and CAVLC Entropy coding
- Easy to integrate and hence faster time-to-market
Deliverables
- Source Code or Netlist
- Simulation Model
- Hardware Test Platform
- Build Scripts
- Test Reports
- User Manual
- Design Documentation
- Constraint Files
- Test Benches
- Support for one year
Applications
- Broadcast
- Video Contribution & Distribution decoders
- Multi-format digital receivers (IRDs)
- Video Wall and Digital Signage
- High End Consumer Electronics
- Test & Measurement Equipment’s
- Aerospace & defense
- Medical
Block Diagram of the H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits
View H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits full description to...
- see the entire H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits datasheet
- get in contact with H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits Supplier
H.264 HD DECODER
- CODA7L - H.264 HP, VC-1 AP, MPEG-4 ASP, MPEG-2 MP, RV8/9/10, VP8, AVS up to 1080p 30fps for decoder and H.264 BP, MPEG-4 SP, H.263 P3 up to 1080p for encoder
- H.264 Video Over IP – HD Decoder Subsystem
- HD H.264 decoder
- AV1 fixed function HW decoder IP for 4Kp60 4:2:0 10 bit
- H.264, MVC, VP8, MPEG-1/2/4, VC-1(WMV), RV(RMVB), AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0
- Low-Latency AVC/H.264 Baseline Profile Decoder Core